Verification intellectual property (IP) is one or more standards-compliant, plug and play modules that can be used to accelerate the development of a complete verification environment to cut down the time to a first test of an electronic design. A verification IP can consist of functional coverage blocks, bus functional models, traffic generators, and protocol monitors and can cut down overall verification time for engineers using different hardware verification language (HVL). Verification IP solutions enable verification engineers to focus on verifying their designs rather than spending an excessive amount of time setting up complex verification environments.
Oftentimes chips are too complex to verify with logic simulation software. A system-on-chip (SoC) including tens of millions of logic gates can overwhelm software simulators, even when running on the fastest servers. Simulating big designs requires hardware-assisted verification, an approach that uses special-purpose hardware to dramatically improve simulation performance. Just as simulation VIP simplifies traditional logic simulation, accelerated VIP makes hardware-assisted verification easier and more productive.
Accelerated VIPs (AVIPs) are used to funnel data to user's design-under-test (DUT) and respond to stimulus received from the DUT. Monitor functions such as collecting coverage and setting callbacks are not included. Tuned for performance, AVIPs are an integral part of a simulation acceleration environment, speeding up verification tens to thousands times relative to simulation. AVIP developers who develop their own transactors often face situations where moving part of the functionality implemented in hardware to software provides better verification capabilities. Conventional options include using direct programming interface (DPI) tasks and standard co-emulation modeling interface (SCE-MI) pipes to create new software and hardware modules to replace and/or augment an existing functionality. The SCE-MI interface can optimize performance and functionality when providing a transactional interface. The DPI tasks and SCE-MI interfaces, while performing well for their intended purposes, can be cumbersome to use and may require significant investment in terms of developer time.